Questions tagged as 'vhdl'

I'm exploring a little bit about FPGA and wanted to do something pretty simple, a button that when clicked would change status . Ignoring the other problems in logic itself, the fact that caught my attention was that it does not even "c...

I've done an algorithm in vhdl and my program is not compiling, it takes an average of 30 minutes up to an hour and gets stuck in the 80%, I do not know why, I'm using the version of quartus 13.01, and the my machine is not bad I have an intel c...

I made a small snippet of code to test the quartus, but this one giving error and I do not know how to solve, the error comes when I compile my excerpt. code snippet: library IEEE; use IEEE.std_logic_1164.all; entity Projeto is port ( a :...

I have a vector in Verilog of 3 bits. I'm tempted to make it range from 000 to 111, simulating on ModelSim. Then I did the following process: Step 1: Step2: Step3: Step4-Part1: Step4-Part2: Step4withthevisualizationofthesignalsofeachindexoft...

Hello, I am trying to make a VHDL ROM where a certain amount of bytes is stored and, upon receiving a clock pulse, one of the values is read and sent to the output while the memory counter is incremented by +1 . The problem I checked is that the...