Error in Quartus II

I made a small snippet of code to test the quartus, but this one giving error and I do not know how to solve, the error comes when I compile my excerpt.

code snippet:

library IEEE;
use IEEE.std_logic_1164.all;
entity Projeto is port
(
 a : in std_logic;
 b : in std_logic;
 c : out std_logic
);
end Projeto;
architecture hard of Projeto is
begin

c <= a AND b;
end hard;

errors:

Error: The core supply voltage value of '1.0V' is illegal for the currently selected part.
Error: Quartus II Fitter was unsuccessful. 1 error, 0 warnings
    Error: Peak virtual memory: 288 megabytes
    Error: Processing ended: Fri Nov 16 15:08:11 2018
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings