My VHDL code never compiles

I've done an algorithm in vhdl and my program is not compiling, it takes an average of 30 minutes up to an hour and gets stuck in the 80%, I do not know why, I'm using the version of quartus 13.01, and the my machine is not bad I have an intel core i7-5500U with 8GB of RAM, I tried to do some methods to speed up the build process a bit but it still keeps on the same percentage, I do not know if it's because my code is not very well built , even because I do not handle much of vhdl, if anyone can help me I would appreciate it.

NOTE: My code is very simple to speak the truth, I need to get an input of a number of 8 bits, and return the largest prime number within the input range (for example if the input is 10, I need return the largest cousin within the range of 1 to 10), I was able to do a similar code in python, I do not understand why I can not compile it in vhdl.

My vhdl code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity maior_primo is port(
  n : in std_logic_vector(7 downto 0);
  s : out std_logic_vector(7 downto 0)
 );
end maior_primo;

architecture Behavioral of maior_primo is
    signal maxtx : integer;
   signal k : natural := 1;

    function maiorpri(limit : natural) return integer is
      variable c : natural;
      variable l : natural := 1;
      variable max : integer;
      constant m : natural := limit;
    begin
      for i in 1 to 10 loop
        c := 0;
        for j in 1 to 10 loop
            if (k mod l) = 0 then
                c := c + 1;
            elsif c = 2 then
                max := k;
                exit;
            end if;
            l := l+1;
            exit when j = m;
        end loop;
        k <= k+1;
        exit when i = m;
      end loop;

      return max;
    end function;
begin
process(n)
begin
   maxtx <= to_integer(unsigned(n));
   s <= std_logic_vector(to_unsigned(maiorpri(maxtx),s'length));
end process;

end Behavioral;