Makefile compile all .c files without specifying them

I'm trying to create a Makefile that causes all .c files to be compiled without having to add the files to the Makefile line by line in the Makefile. I tried to follow the Creating Makefile file , but found it very confusing. My interest is the same:

1 - Check if all .c files have their .o equivalents

2 - Not having .o , create it from the name of the file .c , before checking its files .h headers.

My current Makefile:

BIN     = ./bin
OBJ     = ./obj
INCLUDE = ./include
SRC     = ./src

all:
    gcc -c "$(SRC)/Distancias.c" -o "$(OBJ)/Distancias.o"
    gcc -c "$(SRC)/ManipulaVetores.c" -o "$(OBJ)/ManipulaVetores.o"
    gcc -c "$(SRC)/Classificador.c" -o "$(OBJ)/Classificador.o"
    gcc -c "$(SRC)/ManipulaArquivos.c" -o "$(OBJ)/ManipulaArquivos.o"
    gcc -c testes.c -o "$(OBJ)/main.o"
    gcc -o $(BIN)/main.exe $(OBJ)/*.o -lm

run:
    $(BIN)/main.exe

clean:
    del /F /Q "$(OBJ)" ".o"
    del /F /Q "$(BIN)" ".exe"

I would like to do something like $(SRC)/*.c , but I know it's not that simple because it's not possible to name .o .

As for clean , I've looked for all kinds of commands and I have not found a way to make it work on different platforms. As I'm on Windows, I'm using del .