ISA x Performance


How can the number of instructions (ISA) affect the performance analysis of a system? Can the compiler help in improving the results?

asked by anonymous 31.03.2018 / 05:32

1 answer


ISA stands for " Instruction Set Architecture " - " Instruction Set Architecture ". There are two types of architectures to consider: RISC and CISC.

The CISC stands for "Complex Instruction Set Computer " - " Complex Instruction Set Computer ". This type of computer has several types of microinstructions encoded inside the processor. Sometimes the number of different types of instructions is in the hundreds, and often they have quite different shapes and sizes. However, due to the large number of instructions, the processor design becomes quite complicated and the instructions can take some meaningful time to be decoded and interpreted, most of them taking several clock cycles to complete.

RISC means " Reduced Instruction Set Computer " - " Reduced Instruction Set ". This type of computer has only a few types of microinstructions encoded inside the processor. Because of this, these instructions are uniform in shape and size, which also greatly simplifies processor design and simplifies decoding and execution. Sometimes all or almost all of them take the same time to execute.

There is also a hybrid architecture, which consists of a two-tier processor, the external CISC and the internal RISC. In this processor, each CISC instruction is translated into a sequence of RISC statements that are then executed. Coded in processor circuits, there is a table called microcode that is used to translate each CISC instruction into a sequence of RISC instructions.

Other architectures are also possible, especially in parallel processing.

Note that this says nothing about performance. Having a large number of possible instructions makes each one of them extremely optimized for best performance, allowing the compiler when it generates code, a wide range of possible instructions to choose and combine. But this greatly complicates the design of the processor and can bring a cost in performance because of complexity. With the instruction set reduced, a greater number of instructions need to be executed to do some useful work, but these instructions are quite simple.

Any algorithm to perform some task, when written in a sequence of CISC instructions, is usually much smaller than in a sequence of RISC instructions. The reason for this is precisely because a CISC statement typically represents the work done by several RISC statements. But that does not mean that it is faster or that it is not.

Anyway, no approach is inherently better than the other. To understand, imagine the following: John and Mary are in a competition to see who fills a water tank 1000 liters faster. Every 10 minutes, John dumps a bucket that has an average of 20 liters of water (sometimes more, sometimes less) in his box. Every 3 seconds, Maria dumps a cup with exactly 100 ml in her box. At this pace, both take 8 hours and 20 minutes to finish, drawing. In this approach, each dump in the water tank corresponds to an instruction executed and the amount of water dumped represents the amount of work performed by that instruction, with John using an analogous approach to the CISC and Maria an analogue to the RISC. There is not a clearly better approach to performance.

As for the compiler, it is the one that produces the sequence of instructions to execute, so it is the responsibility of the compiler to determine which instruction sequence to perform the task described in the program being compiled that would result in the best performance. Obviously, this is not a simple matter, but it does mean that his role in improving the analysis of results is critical. A CISC compiler has a much wider range of possible instructions to choose from, which also means that it is much more difficult to know what the best possible sequence of instructions to emit. The RISC compiler has more uniformity in the instructions to be issued, which simplifies the analysis, but probably means producing longer instruction sequences.

31.03.2018 / 07:40