It may be a pretty silly question, but I've researched it and found nothing in the way I'm thinking. I'm studying UML in college, and although it's just dragging the components to form the diagrams, this procedure can be a bit annoying (especially having to be organizing everything).
There are hardware description languages (such as VHDL and Verilog), in which you describe the circuit to be generated, similar to a programming language. So I was thinking that maybe it would be easier for analysts to create UML diagrams in a similar way ...
Is there something like this for UML?