Execution of Instructions

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Execution of Instructions

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#1 by (4 votes)
#2 by (1 votes)

4

I'm reading a book on Introduction to Computer Architecture.

A section of the book reads as follows about the RISC interface of processors: "Each instruction typically takes a clock cycle."

But the same book contains the following excerpt, in Verilog language:

always @(positiveclockedge clk )
begin
    case ( state )
        STATE_FETCH:
            begin
              fetch;
              state = STATE_DECODE;
            end
        STATE_DECODE:
            begin
                decode;
                state = STATE_EXECUTE;
            end
        STATE_EXCUTE:
            begin
                execute;
                state = STATE_FETCH;
            end
    endcase
end

According to the Verilog snippet, even RISC processors take at least 3 clock cycles for an instruction (ignoring any memory access delay yet). Can anyone give me a light on this subject as there is an apparent contradiction (have I noticed this in other texts I have read)?

assembly arquitetura-computadores

asked by anonymous 25.11.2014 / 14:00

2 answers

1

Normally you have a pipeline architecture on fetch - decode - execute - write (RISC) processors. Instructions are executed in a single cycle. But the entire pipeline may take more cycles depending on the architecture you want to deploy.

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26.11.2014 / 17:37

PDO :: rowCount () returning -1 Is there a standard "stack" data structure in Python?

score 4 · Accepted Answer

Generally, processors do not execute an entire statement in a single clock cycle. But at the same time they execute one instruction per clock cycle. How is this possible? Pipeline!

Asyoucanseefromthegraph,onaverageoneinstructionhasjustbeenexecutedforeachclockcycle,generatingthefallacyof1instruction=1cycle.

Ineachcycle4instructionscanbeexecutedsimultaneously.This,ofcourse,inaprocessorthatdividesthepipelineinto4parts,maybeadifferentamount.Anditisforthisreasonthatitissoimportantthattheprocessorcanpredictwhatthenextinstructionwillbeevenbeforeitfinishesthecurrentinstruction(# >).

This division of tasks into parts allows faster processors with reduced clock time. The difficulty appears in trying to make sure that the subsequent statements are valid and can be executed in this way. If for example an instruction writes to the recorder and the next instruction reads from that same recorder, we have a conflict, we can not execute "in parallel" in the pipeline. Some processors are even able to reorder instructions to minimize wait times.